Regviz

Microchip Technology /ATSAME70N21 /QSPI /IDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IDR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J20/QSPI/IDR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RDRF)RDRF 0 (TDRE)TDRE 0 (TXEMPTY)TXEMPTY 0 (OVRES)OVRES 0 (CSR)CSR 0 (CSS)CSS 0 (INSTRE)INSTRE

Description

Interrupt Disable Register

Fields

RDRF

Receive Data Register Full Interrupt Disable
TDRE

Transmit Data Register Empty Interrupt Disable
TXEMPTY

Transmission Registers Empty Disable
OVRES

Overrun Error Interrupt Disable
CSR

Chip Select Rise Interrupt Disable
CSS

Chip Select Status Interrupt Disable
INSTRE

Instruction End Interrupt Disable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data